This invention relates generally to methods of forming field effect transistors, and more specifically to methods for forming field effect transistors having implanted Vt adjust regions and minority carrier barrier regions.
Generally a field effect transistor or FET encompasses a gate structure, source/drain regions operably adjacent the gate structure and a channel region under the gate structure and between the source/drain regions. The gate structure can encompasses a conductive electrode and an insulative layer or gate dielectric disposed between the electrode and the channel region, where each of the gate electrode and gate dielectric can encompass one or more appropriate layers and/or materials. For example, some gate electrodes include a conductively doped polysilicon layer and one or more strapping layers formed of titanium silicide, tungsten nitride and the like. Generally, the gate structure is formed overlying a substrate and the channel and source/drain regions are formed within the substrate, although other constructs are known. While many factors influence and or control the operation of such a FET, one of the more important factors is the physical gate length L, which is generally understood to be the spacing between the source/drain regions of a FET and is a starting point for determining the effective gate length.
Reducing the gate length of FETs generally results in increased switching speeds and makes possible both lower operating voltages and increases in the functional density of integrated circuits that have many thousands of such FETs. However, as L becomes smaller, some issues that are detrimental to FET performance can become problematic. One such issue is transistor sub-threshold leakage that results in current drain in the transistor off state.
Several methods for controlling such sub-threshold leakage are known. Such methods generally involve the performing of one or more ion implant steps to (1) form doped regions in the channel region, (2) modify doping profiles both laterally and elevationally in the channel and source/drain regions and (3) form additional doped regions that can serve to shape and control the flow of electrons and holes that make the operation of such FETs possible.
While the control of sub-threshold leakage is a concern for essentially all FETs, as L is reduced such leakage can be problematic in memory integrated circuits, for example, dynamic random access memory or DRAM circuits. Such DRAM circuits generally contain as many as millions of DRAM cells that each have a FET and a charge storage device, the FET controlling access to the stored charge. Where sub-threshold leakage is relatively high, the stored charge can rapidly dissipate and thus effect the frequency with which the stored charge need be refreshed. Where refresh rates are unnecessarily high, overall performance of the DRAM is reduced.
One feature of merit for DRAM performance is the xe2x80x9cdrain-induced barrier loweringxe2x80x9d (DIBL) effect versus junction leakage on the storage node side of a device. Parametrically this can be viewed as sub-threshold leakage versus xe2x80x9csource/drain diode leakage.xe2x80x9d While reducing the physical gate length can effect threshold voltage or Vt, such can also be effected by the dopant concentration in the channel region as well as that in the source/drain regions. Generally, high dopant density is desirable to reduce sub-threshold leakage (DIBL or sub-Vt), while low dopant density and/or graded junctions are desirable to reduce the diode or junction leakage. Increasing source/drain dopant concentration for improving DIBL, thus generally increases leakage current for both the junctions and between proximate FETs. Thus rather than just a single ion implant for forming source/drain regions, often source/drain regions are engineered to consist of a number of regions such as lightly doped drain (LDD) regions, halo regions and the like to achieve a desired balance between sub-threshold leakage and diode junction leakage.
While the use of ion implantation to form the various doped regions discussed above is well known, generally such implants are done early in the fabrication process of the FET. Thus, control of such regions is hampered by thermal processing that is needed to form the gate structure and other features of the FET. As a result, where a Vt adjust region having a specific peak dopant concentration is desired at a specific location in the channel area of a FET, the thermal processing needed to subsequently form the gate structure generally is xe2x80x9cfactored inxe2x80x9d to achieve the desired result. In addition, often one implantation can effect the result of another prior or subsequent implantation thus adding complexity to the fabrication process. For example, a Vt implant prior to forming the gate structure will place dopant in areas where source/drain regions are to be received and thus is generally xe2x80x9cfactored-inxe2x80x9d to achieve a desired result for such source/drain regions, when formed. Unfortunately, such xe2x80x9cfactoringxe2x80x9d increases the difficulty of providing the desired dopant concentration or desired location of a region. As additional regions are designed to overcome problems that result from the scaling downward in FET size, xe2x80x9cfactoringxe2x80x9d becomes even more difficult.
Therefore it would be advantageous to have methods for forming FETs and DRAM or other memory circuitry that. provides for the elimination or reduction in the complexity of forming such devices. It would be also be advantageous to have methods that reduce or eliminate the effect of one ion implantation on another ion implantation or the effect of subsequent thermal processing on the result of an ion implantation. Additionally, it would be advantageous to have methods that reduce the number of such ion implantation steps conducted in the forming of such FETs and DRAM or other memory circuitry.
The invention includes methods of forming field effect transistors and DRAM circuitry. In one embodiment, in accordance with the present invention, a patterned transistor gate stack is at least partially formed over a semiconductor substrate. The patterned gate stack has opposing sidewalls and at least partially defines a channel region therebeneath within the semiconductor substrate. Ion implanting is conducted through the patterned gate stack to within the semiconductor substrate to form a Vt adjust region of the transistor within the channel region. After the ion implanting, insulative spacers are formed over the gate stack sidewalls. Source/drain regions are at least. partially formed operably proximate the channel region.
In another embodiment of the invention, transistor gate material is formed over a semiconductor substrate and photosensitive masking material is provided over the transistor gate material. The masking material is patterned to form a desired transistor gate outline. With the patterned masking material received over the transistor gate material, exposed transistor gate material is etched effective to at least partially form a patterned transistor gate stack and to at least partially define a channel region therebeneath within the semiconductor substrate. After the etching and with the patterned masking material still in place, ion implanting is conducted through the patterned masking material and the patterned transistor gate stack to within the semiconductor substrate to form a Vt adjust region of the transistor within the channel region. Source/drain regions operably proximate the channel region are formed.
In another embodiment, a patterned transistor gate stack is at least partially formed over a semiconductor substrate. The patterned gate stack has opposing sidewalls and at least partially defines a channel region therebeneath within the semiconductor substrate and at least partially defines opposing source/drain areas. Ion implanting is conducted through the patterned transistor gate stack and into the source/drain areas to within the semiconductor substrate to simultaneously form a Vt adjust region of the transistor within the channel region and respective minority carrier barrier regions to be received within the semiconductor substrate spaced below source/drain regions. Source/drain regions are formed within the source/drain areas operably proximate the channel region. Other embodiments in accordance with the present invention are contemplated, disclosed and claimed hereinbelow.